This invention relates to chip carriers generally and is more particularly concerned with leadless chip carriers.
With the increasing size of large scale integrated circuit chips, the number of input and output connections that have to be made to a chip has correspondingly increased. This trend has encouraged the evolution from dual in-line chip packages, which have two parallel rows of connection pins, to smaller and more dense leadless chip carriers. Leadless chip carriers generally consist of a package containing a square plate of ceramic, such as alumina, which forms a substrate or base onto which a chip is mounted. Electrical connection paths within the leadless chip carrier allow the leads of the chip to be brought to external contact pads formed around each of the four sides of the ceramic base of the carrier. Some leadless chip carriers may even include contact pads formed on the bottom surface of the carrier to utilize the area beneath the chip. The carrier also must provide a thermal conduction path for the enclosed chip and is an important design consideration. The chip carrier is then surface mounted, usually onto a generally larger printed circuit (pc) board or other ceramic board, simply by placing the carrier on top of corresponding contact pads which mirror those contact pads of the chip carrier. An electrical and mechanical connection is then made by soldering the chip carrier to this generally larger board by reflow soldering. This arrangement is less cumbersome than mounting dual in-line packages onto a board and allows greater density of input and output connections to be achieved.
Disadvantages do, however, arise with leadless chip carriers because of the way in which they are connected to a board. Unlike dual in-line packages, where connection is made through relatively flexible pins, the leadless chip carrier is rigidly joined to a generally larger pc board, or other ceramic board, and lacks any ability to accommodate relative movement between the carrier and the board onto which it is mounted. If the chip carrier and the board are of materials having different coefficients of thermal expansion, changes in temperature will cause differential expansion between the two components. This induces strain on the soldered connections, which can cause failure of the electrical and mechanical connection, especially after repeated thermal cycling. In severe cases, such thermal cycling can cause the chip carrier to become detached from the board onto which it is mounted. Studies have been made to determine how to minimize such mounting problems without leading to compromises in other aspects of the design. For example, it is known that small ceramic chip carriers operate more reliably in a thermal cycling environment than larger chip carriers, especially when these are mounted onto a printed circuit board. Therefore, it is clear that if a designer seeks to improve the overall reliability of a mounted ceramic chip carrier package, the designer must attempt to reduce the size of the chip carrier.
One known arrangement for a chip carrier utilizes thick-film techniques to form a pattern of screened-on metallic paste on the surface of an unfired ceramic substrate. Through-holes in this ceramic substrate are filled with a conductive glass-metal paste combination and connect with electrical conductors formed by the pattern of screened-on metallic paste. This ceramic substrate then has a second ceramic layer added beneath it having contact pads on its bottom surface and separated from the conductors and die mount pad on the first ceramic layer. The size and density realizable for such a co-fired chip carrier, while utilizing the center area beneath the die mount pad, is limited by the additive co-fired process itself in that the narrowest conductor width which can be screened is 5 mils, or millinches, with a typical production width being 8 mils wide. Such constraints limit the size and density possible for a chip carrier manufactured using this co-fired method, and they in turn constrain further desired improvements in reliability and in cost.
Various other arrangements have been proposed to improve the reliability while reducing the overall size and manufacturing cost of a chip carrier, but these have not yet proved successful in overcoming each and every other limitation at the same time.